1. Field of the Invention
The present invention relates to an automatic placement and routing apparatus and an automatic placement and routing method. In particular, the invention relates to an automatic placement and routing apparatus and an automatic placement and routing method, with which when modification of logical connection becomes necessary after placement and routing, such modification can be made efficiently.
2. Description of the Background Art
In the manufacturing of a semiconductor device, when creating a mask layout pattern, placement of a plurality of cells (basic circuits) and preparation (wiring) of wiring pattern between cells are performed by automatic placement and routing on the basis of predetermined logical connection information, while modifications to the logical connection information may be needed after placement and routing. This necessitates replacement and rerouting.
Corrections to placement and routing should be avoided if possible. However, in such corrections, it is desirable to make them efficiently. For example, Japanese Patent Laid-Open No. 2001-210717 (the 9th to 15th columns, FIGS. 1 to 9) discloses the technique of reducing the number of manufacturing steps necessary for corrections to placement and routing from back annotation result by hierarchically forming a specific region.
General automatic placement and routing apparatuses often employ the configuration of executing replacement and rerouting to portions requiring no replacement and rerouting. This causes the problem of spending meaningless time for placement and routing, thus making the apparatuses less efficient.
There has also been the problem that unnecessary placement and routing varies the delay time of signals, and a path causing no timing error in the automatic placement and routing before modifying logical connection information becomes a path causing timing error in the automatic placement and routing after modifying the logical connection information.